1. Field
The present disclosure pertains to the field of computing and computer systems, and, more specifically, to the field of performing operations using more than two source values.
2. Background
Instructions used in some computers or processor architectures may identify source operands upon which to perform certain operations, such as load, store, or mathematical operations. Furthermore, the source operands may be identified by either an address of where they are stored or by the operand value itself (i.e., “immediate” value). Some instructions may identify two or more sources to be used in an operation prescribed by an instruction.
For example, some instructions, such as one that performs addition between two or more operands may identify three sources: a base address of a first operand, an index address of the first operand, and a second operand (immediate). Other instructions may identify other operands. Furthermore, depending on the architecture of a processor, the instructions may include sub-instruction operations, or “micro-operations” (“uops”), which identify three or more sources. For the purposes of this disclosure, “instruction”, may be used to mean a macro-level instruction having one or more uops or the term “instruction” may be used to refer to a uop. In some processors, an instruction or uop that identifies three or more sources upon which to perform operations may require logic (hardware circuits and/or software) having three or more inputs, or “ports”, and/or additional overhead to concurrently manage the performance of the prescribed operation pertaining to the three sources.
FIG. 1 illustrates a prior art processor architecture, in which a decoder unit is to receive and decode an instruction or uop identifying at least three sources, and stores the instruction or uop into a front-end queue to be accessed by the execution unit, which may include logic to perform out-of-order execution or in-order execution of instructions or uops. The execution unit, of which there may be multiple, may have three or more input ports and corresponding logic to handle the concurrent processing of the three or more sources identified by an instruction or uop. Instructions may be committed to processor state after the retirement unit retires the instructions or uops.
Unfortunately, the processor architecture (which may include other elements or stages), may require additional logic, such as read ports, etc., to support the processing of instruction or uops identifying three or more sources. Accordingly, the processor architecture may require extra die area, power consumption, etc., in order to support the instructions or uops identifying three or more sources.